1. Field of the Invention
The invention relates to a semiconductor memory device, specifically, relates to a rewritable nonvolatile memory device having a SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) structure, such as a flash memory.
2. Description of the Related Art
One of the most well-known rewritable nonvolatile semiconductor memories is a flash memory having a SONOS structure. Such a flash memory having the SONOS is disclosed in Japanese Patent Publication Reference 2006-184873A.
A flash memory having a SONOS structure disclosed in Japanese Patent Publication Reference 2006-184873A is explained as follows with reference to FIG. 5. FIG. 5 is a cross-sectional view of the conventional single nonvolatile semiconductor memory. As shown in FIG. 5, a memory 110 having the SONOS structure includes a bottom oxide layer 142, a charge-storage film 144 and a top oxide layer 146, which are formed in that order on a silicon substrate 120 at an active region, which is defined by the isolation regions. The bottom oxide layer 142 is also called a tunnel oxide layer, and the top oxide layer 146 is also called a blocking oxide layer.
The memory 110 further includes a gate electrode 138 on the top oxide layer 146. A first and a second diffusion layers 128a and 128b are formed at the surface of the silicon substrate 120 wherein a channel region formed under the gate electrode 138 is sandwiched by the first and the second diffusion layers 128a and 128b. The first and the second diffusion layers 128a and 128b act as a source and a drain or a drain and a source. In the following explanation, the first diffusion layer 128a acts as the drain, and the second diffusion layer 128b acts as the source. Thus, in some occasions, the reference 128a is referred as the drain, and in other occasions, the reference 128a is referred as the first diffusion layer. As well, in some occasions, the reference 128b is referred as the source, and in other occasions, the reference 128b is referred as the second diffusion layer.
The injection of electrons into the charge-storage film 144 is made by applying the ground potential to the source 128b and the silicon substrate 120, and by applying the positive potential to the gate electrode 138 and the drain 128a. Under this condition, hot electrons having a high energy state are generated from the electrons ran in the channel of the silicon substrate 120 under the gate electrode 138 by a strong electric field in the horizontal direction at an area adjacent to the drain 128a. The hot electrons are injected into the charge-storage film 144 by an electric field generated between the gate electrode 138 and the silicon substrate 120.
A condition of the memory 110 is identified by the following states; the state that the electrons are stored in the charge-storage film 144 is indicated as “1”, and the state that the electrons are not stored in the charge-storage film 144 is indicated as “0”
The charge-storage film 144 induces the positive charges at an area of the silicon substrate 120, which is underneath the charge-storage film 144. As a result, the channel resistance increases. Therefore, when the electrons are injected into the charge-storage film 144, the channel current value gets smaller because the channel resistance increases, compared with the condition that the electrons are not injected into the charge-storage film 144. Accordingly, by measuring the size of the channel current value, the condition of the memory 110 whether or not the charge-storage film 144 stores the electrons can be identified.
The size of the channel current value at the time of reading-out the data is determined by the resistance of the source 128b, that is, a condition whether or not the electrons are stored in the charge-storage film 144 at its certain area which is adjacent to the source 128b. Since the charge-storage film 144 can store the electrons locally, it is possible to store the electrons in the charge-storage film 144 either at the source side or at the drain side or both at the source and drain sides. In the memory 110 having the SONOS structure, 2-bit information can be stored in the single memory cell by changing the function of the first diffusion layer 128a from the drain to the source.
However, shorter the gate length of the MOSFET is, shorter the distance between the areas in the charge-storage film 144 of the memory 110 where the electric charges are sorted is. Under this condition, it is hard to store 2-bit information in the single charge-storage film because these two areas cause interference to each other.
To solve this problem, a side-wall type nonvolatile semiconductor memory whose charge-storage layers are formed at the both sides of the gate electrode is proposed. Such a side-wall type memory is referred in Japanese Patent Publication Reference 2005-64295A.
A side-wall type memory disclosed in Japanese Patent Publication Reference 2005-64295A is explained as follows with reference to FIG. 6. FIG. 6 is a cross-sectional view of the conventional single side-wall type memory 210. The side-wall type memory 210 includes a MOS Field Effect Transistor (MOSFET) formed on a silicon substrate 220. The MOSFET includes a gate electrode 238, a first and a second diffusion layers 228a and 228b, and a first and a second resistance changeable layers 227a and 227b. 
The gate electrode is formed on the silicon substrate 220 via a gate oxide layer 236. The first and the second diffusion layers 228a and 228b whose N-type impurities are doped are formed at the surface of the silicon substrate 220 wherein a channel region formed under the gate electrode 238 is sandwiched by the first and the second diffusion layers 228a and 228b. The first and the second diffusion layers 228a and 228b act as a source and a drain or a drain and a source. In the following explanation, the first diffusion layer 228a acts as the drain, and the second diffusion layer 228b acts as the source. Thus, in some occasions, the reference 228a is referred as the drain, and in other occasions, the reference 228a is referred as the first diffusion layer. As well, in some occasions, the reference 228b is referred as the source, and in other occasions, the reference 228b is referred as the second diffusion layer.
The first resistance changeable layer 227a is formed between the first diffusion layer 228a and a channel region 220a, which is formed under the gate electrode 238, and the second resistance changeable layer 227b is formed between the second diffusion layer 228b and the channel region 220a. In both of the first and the second resistance changeable layers 227a and 227b, although N-type impurities, which is the same conductivity type doped in the first and the second diffusion layer 228a and 228b, are doped, the concentration of the impurities' in the first and the second resistance changeable layers 227a and 227b is lighter than that in the first and the second diffusion layer 228a and 228b. 
The side-wall type memory 210 includes a first charge-storage layer 240a formed on the first resistance changeable layer 227a and a second charge-storage layer 240b formed on the second resistance changeable layer 227b. The first charge-storage multi-layer 240a, which is a structure storable electric charges, includes a bottom oxide layer 242a, a charge-storage film 244a, and a top oxide layer 246a, which are formed in that order. The second charge-storage multi-layer 240b, which is a structure storable electric charges, includes a bottom oxide layer 242b, a charge-storage film 244b, and a top oxide layer 246b, which are formed in that order.
According to the side-wall type memory 210, the resistance value of each of the first and the second resistance changeable layers 227a and 227b are changed by the condition whether or not the electric charges are stored in one of, both of or none of the first and the second charge-storage multi-layers 240a and 240b. 
A condition of the memory 210 is identified by the following states; the state that the electrons are stored in the charge-storage multi-layer is indicated as “1”, and the state that the electrons are not stored in the charge-storage multi-layer is indicated as “0”
For example, in order to inject the electrons into the first charge-storage multi-layers 240a, the positive voltage is applied to the gate electrode 238 and to the drain 228a while the source 228b and the silicon substrate 220 are grounded. Under this state, the electrons, which run through the channel, become a high energy condition called “hot electrons” at an area adjacent to the drain 228a by a strong electric field toward the drain 228a. These hot electrons are injected into the first charge-storage multi-layers 240a by an electric field toward the gate electrode 238.
In order to read-out the information at the first charge-storage multi-layers 240a, the positive voltage is applied to the gate electrode 238 and to the source 228b while the drain 228a and the silicon substrate 220 are grounded.
When the electrons are stored in the first charge-storage multi-layers 240a, the electrons stored in the first charge-storage multi-layers 240a induces positive charges in the first resistance changeable layer 227a underneath the first charge-storage multi-layers 240a. The resistance value of the first resistance changeable layer 227a underneath the first charge-storage multi-layers 240a is increased by the induced positive charges so that an electric current between the source and the drain (called “channel current”) is decreased. On the other hand, when the electrons are not stored in the first charge-storage multi-layers 240a, since the resistance value of the first resistance changeable layer 227a is not increased, the channel current is not decreased. By measuring the channel current, it is judged whether or not the electrons are stored in the first charge-storage multi-layers 240a, that is, whether the first charge-storage multi-layers 240a has data “1” or data “0”.
As well as the memory 110 in FIG. 110, in the side-wall type memory 210, two-bit information can be stored in the single memory cell by changing the function of the first diffusion layer 228a from the drain to the source.
However, according to the side-wall type memory 210 disclosed in Japanese Patent Publication Reference 2005-64295A, it is getting difficult to secure the sufficient width for the side wall when the size of the memory cell is shrunken. When the sufficient width for the side wall is not secured enough, the memory cell may have influence of a possible short-channel effect
In response to this demand, some technologies disclosed in Japanese Patent Publication Reference 2004-186663A and Japanese Patent Publication Reference H05-343674A have been proposed. According to these references, the charge-storage layer is located under the surface of the gate oxide layer and the silicon substrate partially. Under the structure of the memory cell disclosed in these references, the substantial channel length can be secured in the vertical direction in the silicon substrate even if the size of the memory cell area is shrunken. Furthermore, in Japanese Patent Reference 3630491 B1, it is disclosed that by forming a poly-silicon electrode on a charge-storage layer, the electric charges are stored in the charge-storage layer by the using its junction capacitance.
However, according to the semiconductor device disclosed in Japanese Patent Publication Reference 2004-186663A and Japanese Patent Publication Reference H05-343674A, a sufficient electric field may not be generated in an area of the silicon substrate, which faces to the charge-storage layer so that a sufficient channel current is hard to obtain. As a result, the judgment for the condition whether the charge-storage layer has data “1” or data “0” may be difficult to make.